Constant-Voltage-Bias Stress Testing of a-IGZO Thin-Film Transistors

Constant-voltage-bias (V DS = V GS = 30 V) stress measurements are performed for a period of 10 5 s on thin-film transistors (TFTs) with amorphous indium-gallium-zinc-oxide (IGZO) channel layers fabricated via RF sputtering using a postdeposition annealing temperature of 200degC, 250degC, or 300degC. Thermal silicon dioxide is employed as a TFT bottom-gate insulator. All SiO 2 /IGZO TFTs tested exhibit the following: 1) a positive rigid log(I D )- V GS transfer curve shift; 2) a continuous drain-current decrease over the entire stress duration; and 3) recovery of the log(I D )-V GS transfer curve toward the prestressed state when the stressed TFT is left unbiased in the dark at room temperature for an extended period of time. The SiO 2 /IGZO TFTs subjected to a higher postdeposition annealing temperature are more stable. A small (and typically negligible) amount of clockwise hysteresis is present in the log(I D ) -V GS transfer curves of IGZO TFTs. These instability and hysteresis observations are consistent with a SiO 2 / IGZO TFT instability mechanism involving electron trapping within the IGZO channel layer.