A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interc...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.18-31
Hauptverfasser:	Stackhouse, B., Bhimji, S., Bostak, C., Bradley, D., Cherkauer, B., Desai, J., Francom, E., Gowan, M., Gronowski, P., Krueger, D., Morganti, C., Troyer, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	65-nm process technology Applied sciences Bandwidth circuit design Circuit synthesis Circuits clock distribution Clocks Communication system control computer architecture Computers, microcomputers Copper Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware High speed Integrated circuit interconnections Integrated circuits Integrated circuits by function (including memories and processors) microprocessor Microprocessors on-die cache Packaging Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Serials Transistors Voltage voltage domains
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Zusammenfassung:	This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2008.2007150