Automatic Constraint Based Test Generation for Behavioral HDL Models : Design verification and validation

Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2008, Vol.16 (4), p.408-421
Hauptverfasser:	SIVA KUMAR SASTRY HARI, VISHNU VARDHAN REDDY KONDA, KAMAKOTI, V, VEDULA, Vivekananda M, MANEPERAMBIL, Kailasnath S
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online-Zugang:	Volltext
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