A 65 nm Embedded SRAM With Wafer Level Bum-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Bibliographische Detailangaben

Hauptverfasser:	OHBAYASHI, Shigeki, YABUUCHI, Makoto, ARAKAWA, Masashi, UCHIDA, Takahiro, OKADA, Masakazu, ISHII, Atsushi, YOSHIHARA, Tsutomu, MAKINO, Hiroshi, ISHIBASHI, Koichiro, SHINOHARA, Hirofumi, KONO, Kazushi, ODA, Yuji, IMAOKA, Susumu, USUI, Keiichi, YONEZU, Toshiaki, IWAMOTO, Takeshi, NII, Koji, TSUKAMOTO, Yasumasa
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors
Online-Zugang:	Volltext
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