FPGA Implementation of a GF(2m) Tate Pairing Architecture
This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve po...
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| creator | Keller, Maurice Kerins, Tim Crowe, Francis Marnane, William |
| description | This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. The performance of the architecture implemented on an FPGA is evaluated for various security levels. |
| doi_str_mv | 10.1007/11802839_44 |
| format | Conference Proceeding |
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P. ; Vassiliadis, Stamatis ; Bertels, Koen</contributor><creatorcontrib>Keller, Maurice ; Kerins, Tim ; Crowe, Francis ; Marnane, William ; Cardoso, João M. P. ; Vassiliadis, Stamatis ; Bertels, Koen</creatorcontrib><description>This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. 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Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Elliptic Curve</subject><subject>Exact sciences and technology</subject><subject>FPGA Implementation</subject><subject>Hardware Implementation</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Security Level</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | Lecture notes in computer science, 2006, p.358-369 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_19968885 |
| source | Springer Books |
| subjects | Applied sciences Circuit properties Clock Cycle Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Elliptic Curve Exact sciences and technology FPGA Implementation Hardware Implementation Integrated circuits Integrated circuits by function (including memories and processors) Security Level Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | FPGA Implementation of a GF(2m) Tate Pairing Architecture |
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