FPGA Implementation of a GF(2m) Tate Pairing Architecture

FPGA Implementation of a GF(2m) Tate Pairing Architecture

This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve po...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Keller, Maurice, Kerins, Tim, Crowe, Francis, Marnane, William
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Circuit properties
Clock Cycle
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Elliptic Curve
Exact sciences and technology
FPGA Implementation
Hardware Implementation
Integrated circuits
Integrated circuits by function (including memories and processors)
Security Level
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Beschreibung
Zusammenfassung:This paper presents a hardware implementation of a dual mode Tate pairing/elliptic curve processor over fields of characteristic 2. The architecture can be reconfigured for different underlying field sizes and hence can support different security levels. The processor also performs elliptic curve point scalar multiplication. The performance of the architecture implemented on an FPGA is evaluated for various security levels.
ISSN:0302-9743
1611-3349
DOI:10.1007/11802839_44