BDD-Based Hardware Verification

This chapter overviewes Binary Decision Diagrams (BDDs) and their application in Formal Hardware Verification. BDDs are first described as a representation formalism for Boolean functions. BDDs are directed acyclic graphs, deriving their efficiency from canonicity, and from their ability to be exponentially more compact, in terms of node count, than alternative Boolean representations. The chapter introduces the main BDD operators, in terms of recursive graph manipulation functions. Some of the most succesful Formal Verification techniques, based on BDD engines, are then reported. The description is limited to Reduced Ordered BDDs (ROBDDs), which, albeight being just one among several decomposition types, are the most widely used and the most general one.