A 15-ns 4-Mb CMOS SRAM

A 15-ns 4-Mb CMOS SRAM

A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (*4 or *1) bit organization has been developed based on a 0.55- mu m triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (T...

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Veröffentlicht in:IEEE journal of solid-state circuits 1990-10, Vol.25 (5), p.1063-1067
Hauptverfasser: Aizaki, S., Shimizu, T., Ohkawa, M., Abe, K., Aizaki, A., Ando, M., Kudoh, O., Sasaki, I.
Format: Artikel
Sprache:eng
Schlagworte:
Application software
Applied sciences
Circuit testing
CMOS memory circuits
CMOS technology
Decoding
Driver circuits
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Large-scale systems
Mirrors
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Beschreibung
Zusammenfassung:A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (*4 or *1) bit organization has been developed based on a 0.55- mu m triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55- mu m CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either *4 or *1 can be selected purely electrically, and does not require any pin connection procedure.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.62125