Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast...

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Hauptverfasser: Pitkänen, Teemu, Mäkinen, Risto, Heikkinen, Jari, Partanen, Tero, Takala, Jarmo
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Mäkinen, Risto
Heikkinen, Jari
Partanen, Tero
Takala, Jarmo
description Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.
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fullrecord <record><control><sourceid>pascalfrancis_sprin</sourceid><recordid>TN_cdi_pascalfrancis_primary_19688878</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>19688878</sourcerecordid><originalsourceid>FETCH-LOGICAL-p219t-beb3874a3c63c9eb333bf95a63ac5ff7acf8192c3067bf147b132c481a1d58143</originalsourceid><addsrcrecordid>eNpNUEtLAzEQji-w1p78A3vxIBjN7GTzOJZirVBoD-t5ycakrrabklSK_96UCjqHGWa-x8BHyA2wB2BMPgJILThWTclPyBVWnKHgAOyUDEAAUESuz_4AVp6TAUNWUi05XpJRSh8sF4JELQZkMQ97ugx7F--LWbd6p0sXfYgb01tX1PW4WMZgXUohFvlcZD-e6V2_K6Ym5Ra-YudiUUfTp4Pumlx4s05u9DuH5HX6VE9mdL54fpmM53Rbgt7R1rWoJDdoBVqdF8TW68oINLbyXhrrFejSIhOy9cBlC1harsDAW6WA45DcHn23Jlmz9vm_7VKzjd3GxO8GtFBKSZV5d0deylC_crFpQ_hMDbDmEGfzL078AbgeYIY</addsrcrecordid><sourcetype>Index Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform</title><source>Springer Books</source><creator>Pitkänen, Teemu ; Mäkinen, Risto ; Heikkinen, Jari ; Partanen, Tero ; Takala, Jarmo</creator><contributor>Hämäläinen, Timo D. ; Vassiliadis, Stamatis ; Wong, Stephan</contributor><creatorcontrib>Pitkänen, Teemu ; Mäkinen, Risto ; Heikkinen, Jari ; Partanen, Tero ; Takala, Jarmo ; Hämäläinen, Timo D. ; Vassiliadis, Stamatis ; Wong, Stephan</creatorcontrib><description>Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 3540364102</identifier><identifier>ISBN: 9783540364108</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 3540364110</identifier><identifier>EISBN: 9783540364115</identifier><identifier>DOI: 10.1007/11796435_24</identifier><language>eng</language><publisher>Berlin, Heidelberg: Springer Berlin Heidelberg</publisher><subject>Applied sciences ; Code Compression ; Electronics ; Exact sciences and technology ; Fast Fourier Transform ; Field Programmable Gate Array ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Twiddle Factor ; Very Long Instruction Word</subject><ispartof>Embedded Computer Systems: Architectures, Modeling, and Simulation, 2006, p.227-236</ispartof><rights>Springer-Verlag Berlin Heidelberg 2006</rights><rights>2007 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/11796435_24$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/11796435_24$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>309,310,775,776,780,785,786,789,4035,4036,27904,38234,41421,42490</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=19688878$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><contributor>Hämäläinen, Timo D.</contributor><contributor>Vassiliadis, Stamatis</contributor><contributor>Wong, Stephan</contributor><creatorcontrib>Pitkänen, Teemu</creatorcontrib><creatorcontrib>Mäkinen, Risto</creatorcontrib><creatorcontrib>Heikkinen, Jari</creatorcontrib><creatorcontrib>Partanen, Tero</creatorcontrib><creatorcontrib>Takala, Jarmo</creatorcontrib><title>Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform</title><title>Embedded Computer Systems: Architectures, Modeling, and Simulation</title><description>Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.</description><subject>Applied sciences</subject><subject>Code Compression</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Fast Fourier Transform</subject><subject>Field Programmable Gate Array</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Twiddle Factor</subject><subject>Very Long Instruction Word</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>3540364102</isbn><isbn>9783540364108</isbn><isbn>3540364110</isbn><isbn>9783540364115</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpNUEtLAzEQji-w1p78A3vxIBjN7GTzOJZirVBoD-t5ycakrrabklSK_96UCjqHGWa-x8BHyA2wB2BMPgJILThWTclPyBVWnKHgAOyUDEAAUESuz_4AVp6TAUNWUi05XpJRSh8sF4JELQZkMQ97ugx7F--LWbd6p0sXfYgb01tX1PW4WMZgXUohFvlcZD-e6V2_K6Ym5Ra-YudiUUfTp4Pumlx4s05u9DuH5HX6VE9mdL54fpmM53Rbgt7R1rWoJDdoBVqdF8TW68oINLbyXhrrFejSIhOy9cBlC1harsDAW6WA45DcHn23Jlmz9vm_7VKzjd3GxO8GtFBKSZV5d0deylC_crFpQ_hMDbDmEGfzL078AbgeYIY</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Pitkänen, Teemu</creator><creator>Mäkinen, Risto</creator><creator>Heikkinen, Jari</creator><creator>Partanen, Tero</creator><creator>Takala, Jarmo</creator><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>IQODW</scope></search><sort><creationdate>2006</creationdate><title>Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform</title><author>Pitkänen, Teemu ; Mäkinen, Risto ; Heikkinen, Jari ; Partanen, Tero ; Takala, Jarmo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p219t-beb3874a3c63c9eb333bf95a63ac5ff7acf8192c3067bf147b132c481a1d58143</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Applied sciences</topic><topic>Code Compression</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Fast Fourier Transform</topic><topic>Field Programmable Gate Array</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Twiddle Factor</topic><topic>Very Long Instruction Word</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pitkänen, Teemu</creatorcontrib><creatorcontrib>Mäkinen, Risto</creatorcontrib><creatorcontrib>Heikkinen, Jari</creatorcontrib><creatorcontrib>Partanen, Tero</creatorcontrib><creatorcontrib>Takala, Jarmo</creatorcontrib><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Pitkänen, Teemu</au><au>Mäkinen, Risto</au><au>Heikkinen, Jari</au><au>Partanen, Tero</au><au>Takala, Jarmo</au><au>Hämäläinen, Timo D.</au><au>Vassiliadis, Stamatis</au><au>Wong, Stephan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform</atitle><btitle>Embedded Computer Systems: Architectures, Modeling, and Simulation</btitle><date>2006</date><risdate>2006</risdate><spage>227</spage><epage>236</epage><pages>227-236</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>3540364102</isbn><isbn>9783540364108</isbn><eisbn>3540364110</eisbn><eisbn>9783540364115</eisbn><abstract>Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.</abstract><cop>Berlin, Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/11796435_24</doi><tpages>10</tpages></addata></record>
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ispartof Embedded Computer Systems: Architectures, Modeling, and Simulation, 2006, p.227-236
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1611-3349
language eng
recordid cdi_pascalfrancis_primary_19688878
source Springer Books
subjects Applied sciences
Code Compression
Electronics
Exact sciences and technology
Fast Fourier Transform
Field Programmable Gate Array
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Twiddle Factor
Very Long Instruction Word
title Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T13%3A50%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-pascalfrancis_sprin&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Low-Power,%20High-Performance%20TTA%20Processor%20for%201024-Point%20Fast%20Fourier%20Transform&rft.btitle=Embedded%20Computer%20Systems:%20Architectures,%20Modeling,%20and%20Simulation&rft.au=Pitk%C3%A4nen,%20Teemu&rft.date=2006&rft.spage=227&rft.epage=236&rft.pages=227-236&rft.issn=0302-9743&rft.eissn=1611-3349&rft.isbn=3540364102&rft.isbn_list=9783540364108&rft_id=info:doi/10.1007/11796435_24&rft_dat=%3Cpascalfrancis_sprin%3E19688878%3C/pascalfrancis_sprin%3E%3Curl%3E%3C/url%3E&rft.eisbn=3540364110&rft.eisbn_list=9783540364115&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true