Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform
Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast...
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creator | Pitkänen, Teemu Mäkinen, Risto Heikkinen, Jari Partanen, Tero Takala, Jarmo |
description | Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency. |
doi_str_mv | 10.1007/11796435_24 |
format | Conference Proceeding |
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This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.</description><identifier>ISSN: 0302-9743</identifier><identifier>ISBN: 3540364102</identifier><identifier>ISBN: 9783540364108</identifier><identifier>EISSN: 1611-3349</identifier><identifier>EISBN: 3540364110</identifier><identifier>EISBN: 9783540364115</identifier><identifier>DOI: 10.1007/11796435_24</identifier><language>eng</language><publisher>Berlin, Heidelberg: Springer Berlin Heidelberg</publisher><subject>Applied sciences ; Code Compression ; Electronics ; Exact sciences and technology ; Fast Fourier Transform ; Field Programmable Gate Array ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Semiconductor electronics. Microelectronics. Optoelectronics. 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This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.</description><subject>Applied sciences</subject><subject>Code Compression</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Fast Fourier Transform</subject><subject>Field Programmable Gate Array</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Twiddle Factor</subject><subject>Very Long Instruction Word</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>3540364102</isbn><isbn>9783540364108</isbn><isbn>3540364110</isbn><isbn>9783540364115</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNpNUEtLAzEQji-w1p78A3vxIBjN7GTzOJZirVBoD-t5ycakrrabklSK_96UCjqHGWa-x8BHyA2wB2BMPgJILThWTclPyBVWnKHgAOyUDEAAUESuz_4AVp6TAUNWUi05XpJRSh8sF4JELQZkMQ97ugx7F--LWbd6p0sXfYgb01tX1PW4WMZgXUohFvlcZD-e6V2_K6Ym5Ra-YudiUUfTp4Pumlx4s05u9DuH5HX6VE9mdL54fpmM53Rbgt7R1rWoJDdoBVqdF8TW68oINLbyXhrrFejSIhOy9cBlC1harsDAW6WA45DcHn23Jlmz9vm_7VKzjd3GxO8GtFBKSZV5d0deylC_crFpQ_hMDbDmEGfzL078AbgeYIY</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Pitkänen, Teemu</creator><creator>Mäkinen, Risto</creator><creator>Heikkinen, Jari</creator><creator>Partanen, Tero</creator><creator>Takala, Jarmo</creator><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>IQODW</scope></search><sort><creationdate>2006</creationdate><title>Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform</title><author>Pitkänen, Teemu ; Mäkinen, Risto ; Heikkinen, Jari ; Partanen, Tero ; Takala, Jarmo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p219t-beb3874a3c63c9eb333bf95a63ac5ff7acf8192c3067bf147b132c481a1d58143</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Applied sciences</topic><topic>Code Compression</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Fast Fourier Transform</topic><topic>Field Programmable Gate Array</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Twiddle Factor</topic><topic>Very Long Instruction Word</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pitkänen, Teemu</creatorcontrib><creatorcontrib>Mäkinen, Risto</creatorcontrib><creatorcontrib>Heikkinen, Jari</creatorcontrib><creatorcontrib>Partanen, Tero</creatorcontrib><creatorcontrib>Takala, Jarmo</creatorcontrib><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Pitkänen, Teemu</au><au>Mäkinen, Risto</au><au>Heikkinen, Jari</au><au>Partanen, Tero</au><au>Takala, Jarmo</au><au>Hämäläinen, Timo D.</au><au>Vassiliadis, Stamatis</au><au>Wong, Stephan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform</atitle><btitle>Embedded Computer Systems: Architectures, Modeling, and Simulation</btitle><date>2006</date><risdate>2006</risdate><spage>227</spage><epage>236</epage><pages>227-236</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>3540364102</isbn><isbn>9783540364108</isbn><eisbn>3540364110</eisbn><eisbn>9783540364115</eisbn><abstract>Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.</abstract><cop>Berlin, Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/11796435_24</doi><tpages>10</tpages></addata></record> |
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identifier | ISSN: 0302-9743 |
ispartof | Embedded Computer Systems: Architectures, Modeling, and Simulation, 2006, p.227-236 |
issn | 0302-9743 1611-3349 |
language | eng |
recordid | cdi_pascalfrancis_primary_19688878 |
source | Springer Books |
subjects | Applied sciences Code Compression Electronics Exact sciences and technology Fast Fourier Transform Field Programmable Gate Array Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Twiddle Factor Very Long Instruction Word |
title | Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform |
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