Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast...

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Hauptverfasser:	Pitkänen, Teemu, Mäkinen, Risto, Heikkinen, Jari, Partanen, Tero, Takala, Jarmo
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Code Compression Electronics Exact sciences and technology Fast Fourier Transform Field Programmable Gate Array Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Twiddle Factor Very Long Instruction Word
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Beschreibung
Zusammenfassung:	Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.
ISSN:	0302-9743 1611-3349
DOI:	10.1007/11796435_24