Synthesized UML, a Practical Approach to Map UML to VHDL

Embedded Systems are complex systems with limited resources such as reduced processor power or relatively small amounts of memory and so on. The real time aspect may also play an important role, but is definitely not a main consideration of this work. Complexity of recent embedded systems is growing as rapidly as the demand for such systems and only can be managed by the use of a model-driven design approach. Since modeling languages such as UML are semi-formal they allow the design of systems that can’t be implemented using formal languages such as C/C++ or VHDL. This paper intends to show how the gap between model and formal language can be bridged. First of all a set of rules restricts the use of model elements in a way that the model will become executable. Furthermore a unique mapping between UML and formal language elements enables automatic code generation. Formal verification at model level is an important consideration and becomes possible by the fact that rules restrict the application of model elements. UML to software (C/C++) and UML to hardware (VHDL) mapping form the base for a practical codesign approach where a part of the system is realized through software and another part trough hardware. Mapping of UML to programming languages is well known today and realized in many tools. Mapping of UML to hardware description languages is less known and not realized in tools. This paper documents an attempt to define a set of rules and to implement UML to VHDL mapping in a practical code generator. It also shows parts of a real world sample that was realized to verify usability and stability of rules and mapping. Finally, an outlook on further developments, improvement of the UML to VHDL mapping and a simple codesign process called 6qx will be given.