The Grand Pareto : A methodology for identifying and quantifying yield detractors in volume semiconductor manufacturing : The advanced semiconductor manufacturing conference

Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on semiconductor manufacturing 2007, Vol.20 (2), p.87-100
Hauptverfasser:	DESINENI, Rao, BERNDLMAIER, Zachary, WINSLOW, Jonathan, BLAUBERG, Alisa, CHU, Benjamin R
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Testing, measurement, noise and reliability
Online-Zugang:	Volltext
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