Minimizing power consumption in scan testing: pattern generation and DFT techniques

Minimizing power consumption in scan testing: pattern generation and DFT techniques

It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically incre...

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Bibliographische Detailangaben
Hauptverfasser: Butler, K.M., Saxena, J., Jain, A., Fryars, T., Lewis, J., Hetherington, G.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Clocks
Design for testability
Electronics
Energy consumption
Exact sciences and technology
Instruments
Lifting equipment
Logic testing
Power demand
Power generation
Production
Test pattern generators
Testing, measurement, noise and reliability
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Beschreibung
Zusammenfassung:It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.
DOI:10.1109/TEST.2004.1386971