Power management for FPGAs: power-driven design partitioning

In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficiency needs to be improved. This paper proposes a power management scheme for FPGAs centered on the power-driven partitioning technique. Power-driven partitioner create clusters within the a design such that within individual clusters, power consumption can be improved via voltage scaling. The aim is to identify subgraphs/partitions in a design, such that the total power consumption is minimised while resource constraints associated with the partitioning problem are satisfied.