Reconfigurable Multiplier for Virtex FPGA Family

Reconfigurable Multiplier for Virtex FPGA Family

This paper describes integer multiplier design optimizations for FPGA technology. The changes in partial product generator component enable to infer CLB fast carry logic for building Wallace trees. This change increases speed and gives better resource allocation.

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Bibliographische Detailangaben
Hauptverfasser: Põldre, Juri, Tammemäe, Kalle
Format: Buchkapitel
Sprache:eng
Schlagworte:
Applied sciences
Computer science
control theory
systems
Computer systems performance. Reliability
Exact sciences and technology
Software
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Beschreibung
Zusammenfassung:This paper describes integer multiplier design optimizations for FPGA technology. The changes in partial product generator component enable to infer CLB fast carry logic for building Wallace trees. This change increases speed and gives better resource allocation.
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-540-48302-1_38