An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems
Recovering the symbols in a multiple-input multiple-output (MIMO) receiver is a computationally intensive process. The layered space-time (LST) algorithms provide a reasonable tradeoff between complexity and performance. Commercial digital signal processors (DSPs) have become a key component in many...
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| Veröffentlicht in: | IEEE transactions on signal processing 2006-10, Vol.54 (10), p.3899-3907 |
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| container_title | IEEE transactions on signal processing |
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| creator | Alimohammad, A. Cockburn, B.F. |
| description | Recovering the symbols in a multiple-input multiple-output (MIMO) receiver is a computationally intensive process. The layered space-time (LST) algorithms provide a reasonable tradeoff between complexity and performance. Commercial digital signal processors (DSPs) have become a key component in many high-volume products such as cellular telephones. As an alternative to power-hungry DSPs, we propose to use a moderately parallel single-instruction stream, multiple-data stream (SIMD) coprocessor architecture, called DSP-RAM, to implement an LST MIMO receiver that offers high performance with relatively low power consumption. For a typical indoor wireless environment, a 100-MHz DSP-RAM can potentially provide more than ten times greater decoding throughput at the receiver of a (4,4) MIMO system compared with a conventional 720-MHz DSP. The DSP-RAM processor has been coded in a hardware description language (HDL) and synthesized for both available field-programmable gate arrays (FPGAs) and for a 0.18-mum CMOS standard cell implementation |
| doi_str_mv | 10.1109/TSP.2006.879326 |
| format | Article |
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The layered space-time (LST) algorithms provide a reasonable tradeoff between complexity and performance. Commercial digital signal processors (DSPs) have become a key component in many high-volume products such as cellular telephones. As an alternative to power-hungry DSPs, we propose to use a moderately parallel single-instruction stream, multiple-data stream (SIMD) coprocessor architecture, called DSP-RAM, to implement an LST MIMO receiver that offers high performance with relatively low power consumption. For a typical indoor wireless environment, a 100-MHz DSP-RAM can potentially provide more than ten times greater decoding throughput at the receiver of a (4,4) MIMO system compared with a conventional 720-MHz DSP. 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| subjects | Algorithms Applied sciences Architecture Coding, codes Coprocessors Decoding Digital signal processing Digital signal processors Exact sciences and technology Field programmable gate arrays Hardware design languages Information, signal and communications theory Layered space-time decoding MIMO multiple-input multiple-output (MIMO) receiver Parallel architectures parallel processing processor-in-memory Processors Receivers Signal and communications theory Signal processing Signal processing algorithms Streams Telecommunications and information theory Telephony |
| title | An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems |
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