An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems

Recovering the symbols in a multiple-input multiple-output (MIMO) receiver is a computationally intensive process. The layered space-time (LST) algorithms provide a reasonable tradeoff between complexity and performance. Commercial digital signal processors (DSPs) have become a key component in many high-volume products such as cellular telephones. As an alternative to power-hungry DSPs, we propose to use a moderately parallel single-instruction stream, multiple-data stream (SIMD) coprocessor architecture, called DSP-RAM, to implement an LST MIMO receiver that offers high performance with relatively low power consumption. For a typical indoor wireless environment, a 100-MHz DSP-RAM can potentially provide more than ten times greater decoding throughput at the receiver of a (4,4) MIMO system compared with a conventional 720-MHz DSP. The DSP-RAM processor has been coded in a hardware description language (HDL) and synthesized for both available field-programmable gate arrays (FPGAs) and for a 0.18-mum CMOS standard cell implementation