Highly area efficient and cost effective double stacked S3(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

Bibliographische Detailangaben

Hauptverfasser:	JUNG, Soon-Moon, LIM, Hoon, KIM, Sungjin, JEONG, Jaehun, CHANG, Youngchul, JANG, Jaehoon, KIM, Jonghyuk, KIM, Kinam, RYU, Byung-Il, CHO, Wonseok, CHO, Hoosung, YEO, Chadong, YONGHA KANG, BAE, Daegi, NA, Jonghoon, KWAK, Kunho, CHOI, Bonghyun
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors
Online-Zugang:	Volltext
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