Cached memory performance characterization of a wireless digital baseband processor

We present performance analysis results of the MSP500 digital baseband (DBB) platform, a system developed at Analog Devices Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which i...

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Hauptverfasser:	Kannaw, S., Allen, M., Fridman, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Baseband Communication standards Digital signal processing Equipments and installations Exact sciences and technology Ground penetrating radar GSM IEEE members Mobile radiocommunication systems Performance analysis Radiocommunications Random access memory Services and terminals of telecommunications Software standards Systems, networks and services of telecommunications Telecommunications Telecommunications and information theory Telephone sets Telephone. Videophone
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Beschreibung
Zusammenfassung:	We present performance analysis results of the MSP500 digital baseband (DBB) platform, a system developed at Analog Devices Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which integrates a Blackfin/spl reg/ core, and examine the execution time performance of a number of wireless physical layer software components from the perspective of an instruction- and data-cached memory hierarchy. The Blackfin is a 16-bit fixed-point core that combines some of the best features of DSPs and micro-controllers, and has support for a cached memory system.
ISSN:	1520-6149 2379-190X
DOI:	10.1109/ICASSP.2004.1327122