A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architecture

This paper describes a 2.2 ns search-time, 0.7 fJ/bit/search 0.1 /spl mu/m CMOS TCAM which uses NOR cells for high-speed coarse search and NAND cells for low-power fine search. A hidden bank selection eliminates the timing penalty for partial activation, a match line repeater enhances the search spe...

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Hauptverfasser: CHOI, Sungdae, SOHN, Kyomin, LEE, Min-Wuk, KIM, Sunyoung, CHOI, Hye-Mi, KIM, Donghyun, CHO, Uk-Rae, BYUN, Hyun-Geun, SHIN, Yun-Seung, YOO, Hoi-Jun
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
CADCAM
Clocks
CMOS process
Computer aided manufacturing
Decoding
Electronics
Energy consumption
Energy efficiency
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Magnetic and optical mass memories
Prototypes
Repeaters
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Storage and reproduction of information
Timing
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Beschreibung
Zusammenfassung:This paper describes a 2.2 ns search-time, 0.7 fJ/bit/search 0.1 /spl mu/m CMOS TCAM which uses NOR cells for high-speed coarse search and NAND cells for low-power fine search. A hidden bank selection eliminates the timing penalty for partial activation, a match line repeater enhances the search speed and column decoding enables high memory density.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2004.1332812