Real-Time System-on-a-Chip Architecture for Rule-Based Context-Aware Computing

A rule-based system can be a solution for context reasoning in context-aware computing systems. In this paper we propose new flexible SoC (System-on-a-Chip) architecture for real-time rule-based system. The proposed architecture can match up values and variables of the left-hand sides of ‘if-then rules’ (rule’s LHS) in parallel. Compared to previous hardware rule-based system, we reduce the number of constraints on rule representations and combinations of condition terms in rule’s LHS by using a modified contents addressable memory and a crossbar switch network (CSN). The modified contents addressable memory (CAM), in which the match operation of the system is processed in parallel, stores the rule-base of the system. The crossbar switch network is located between the input buffer that stores external raw input data and the working memory, and can freely configure condition operation of rule’s LHS and working memory with stored data within the input buffer. The proposed SoC systems architecture has been designed and verified in a SoC development platform called SystemC.