High Speed JPEG Coder Based on Modularized and Pipelined Architecture with Distributed Control

The design of an efficient reusable IP based Extended JPEG encoder is presented in this paper. This encoder uses user-defined quantization and Huffman tables that can be reconfigured at run-time. It has a modularized and pipelined architecture with distributed control for each block. A simple interface makes integration of the modules in various systems simple and straightforward. The design when targeted on FPGA operated at speed of up to 90MHz and when mapped on 0.25μm CMOS process the design can operate at speeds over 450MHz, which is faster than any of the similar JPEG encoder designs reported.