Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators

This paper evaluates two techniques to improve the linearity of the main feedback D/A converter in multi-bit continuous-time sigma-delta modulators (CT-SDM). A self-calibrated current-steering (SCCS) implementation of the D/A converter is compared to the usage of a data-weighted averaging (DWA) algo...

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Hauptverfasser:	Paton, S., Poscher, T., Di Giandomenico, A., Kolhaupt, K., Hernandez, L., Wiesbauer, A., Clara, M., Frutos, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Added delay Applied sciences Bandwidth Circuit properties Circuit testing Clocks Delta-sigma modulation Design. Technologies. Operation analysis. Testing Dynamic range Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Feedback Integrated circuits Integrated circuits by function (including memories and processors) Linearity Modulation coding Sampling methods Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors
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Beschreibung
Zusammenfassung:	This paper evaluates two techniques to improve the linearity of the main feedback D/A converter in multi-bit continuous-time sigma-delta modulators (CT-SDM). A self-calibrated current-steering (SCCS) implementation of the D/A converter is compared to the usage of a data-weighted averaging (DWA) algorithm on the selection of uncalibrated D/A-elements. Two test-chips including the two different solutions are presented and measurement results are compared. Clocked at 300 MHz, the two CT-SDMs achieve a dynamic range of 67 dB (DWA) and 70 dB (SCCS), respectively, over an analog bandwidth of 15 MHz.
DOI:	10.1109/CICC.2004.1358875