Design and implementation of an embedded 512KB level 2 cache subsystem

Design and implementation of an embedded 512KB level 2 cache subsystem

Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 /spl mu/m technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully integrated subsystem is composed of data and tag SR...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Jinuk Luke Shin, Petrick, B., Levy, H., Jinseung Son, Mandeep Singh, Mathur, V., Jung-Cheng Yeh, Heesung Choi, Gupta, V., Ziaja, T., Leon, A.S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Clocks
Delay
Design. Technologies. Operation analysis. Testing
Electronics
Engines
Exact sciences and technology
Frequency
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic
Microprocessors
Pipelines
Protection
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
Transistors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 /spl mu/m technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully integrated subsystem is composed of data and tag SRAMs along with datapaths, controller and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64b microprocessors, with a data latency of only 4 cycles including ECC correction for 128-bit data. The design solutions to build this integrated short latency L2 cache are discussed.
DOI:10.1109/CICC.2004.1358818