Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta 2O 5, HfO 2 and Al 2O 3 as high- k dielectric for use in 65 nm eDRAM technology, Al 2O 3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high- k dielectrics and capacitor electrodes.