Performance improvement of tall triple gate devices with strained SiN layers

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensi...

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Veröffentlicht in:	IEEE electron device letters 2005-11, Vol.26 (11), p.820-822
Hauptverfasser:	Collaert, N., De Keersgieter, A., Anil, K.G., Rooyackers, R., Eneman, G., Goodwin, M., Eyckens, B., Sleeckx, E., de Marneffe, J.-F., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Capacitive sensors Compressive stress Devices Electron mobility Electronics Etching Exact sciences and technology Fabrication FinFET Gates mobility improvement MOS devices MOSFETs Performance enhancement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon compounds strain Tensile stress Thin film transistors Transistors
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Beschreibung
Zusammenfassung:	In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.
ISSN:	0741-3106 1558-0563
DOI:	10.1109/LED.2005.857692