Improved Blocks for CMOS Analog Neuro-fuzzy Network

This paper proposes several improved CMOS analog circuits for neuro-fuzzy network, including Gaussian-like membership function circuit, minimization circuit, and a centroid algorithm defuzzier circuit without using division. A two-input/one-output neuro-fuzzy network composed of these circuits is implemented and testified for non-linear function approximating. HSPICE simulation results show that all the proposed circuits provide characteristics of high operation capacity, high speed, simple structures, and high precision. They are very suitable for rapid implementation of neuro-fuzzy networks.