Efficient Hardware for the Tate Pairing Calculation in Characteristic Three

In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardw...

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Bibliographische Detailangaben
Hauptverfasser:	Kerins, T., Marnane, W. P., Popovici, E. M., Barreto, P. S. L. M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences characteristic three Computer science control theory systems Cryptography Electronics Exact sciences and technology hardware accelerator Information, signal and communications theory Integrated circuits Integrated circuits by function (including memories and processors) Memory and file management (including protection and security) Memory organisation. Data processing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Software Tate pairing Telecommunications and information theory tower fields
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Beschreibung
Zusammenfassung:	In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.
ISSN:	0302-9743 1611-3349
DOI:	10.1007/11545262_30