Packet Classification Algorithm Using Multiple Subspace Intersecting

Packet classification on multi-fields is difficult and has poor worst-case performance due to its character of multiple dimensions. Thus his paper proposes a efficient hardware algorithm MSI (multiple subspace intersecting) to solve it. MSI cuts each dimension of the classifier into several subspaces and then utilizes the parallelism of hardware to do the classification on these subspaces. For a classifier with n rules of width W, MSI needs only less than n[4W+log2(n)] bits. MSI is able to classify 100 M packets/s with pipelined hardware, supports fast incremental update, and has good flexibility in specification of rule and. By simulation, we find MSI has better performance comparing to some existing algorithms.