Wafer-level 3D system-on-a-chip using dielectric glue wafer bonding and Cu damascene inter-wafer interconnects

Bibliographische Detailangaben

Hauptverfasser:	LU, J.-Q, JINDAL, A, GUTMANN, R. J, KWON, Y, MCMAHON, J. J, LEE, K.-W, KRAFT, R. P, ALTEMUS, B, CHENG, D, EISENBRAUN, E, CALE, T. S
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online-Zugang:	Volltext
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