Managing Verification Activities Using SVM

SVM (System Verification Manager) manages the application of verification methods for model-based development of embedded systems by providing integrated representations of requirements, system architecture, models and verification methods. Developed in Java within MATLAB®, SVM supports all types of tools for modelling and verification through an extensible framework of data and coding structures. This paper presents the main features of SVM and illustrates its application to embedded control and signal processing systems.