Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures

This paper presents a methodology and framework to model the behavior of superscalar microprocessors. The simulation is focused on timing analysis and ignores all functional aspects. The methodology also provides a framework for building new simulators for generic architectures. The results obtained...

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Hauptverfasser: Brandolese, C., Fornaciari, W., Salice, F.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:This paper presents a methodology and framework to model the behavior of superscalar microprocessors. The simulation is focused on timing analysis and ignores all functional aspects. The methodology also provides a framework for building new simulators for generic architectures. The results obtained show a good accuracy and a satisfactory computational efficiency. Furthermore, the C++ SDK allows rapid development of new processor models making the methodology suitable for design space exploration over new processor architectures.
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-540-30205-6_26