Secure Logic Synthesis

Secure Logic Synthesis

This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Tiri, Kris, Verbauwhede, Ingrid
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Computer science
control theory
systems
Design Flow
Differential Power Analysis
Electronics
Exact sciences and technology
FPGA Implementation
Integrated circuits
Integrated circuits by function (including memories and processors)
Language processing and microprogramming
Logic Synthesis
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Software
Synthesis Tool
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the slice utilization when compared with a normal non-secure single ended implementation.
ISSN:0302-9743
1611-3349
DOI:10.1007/978-3-540-30117-2_125