A Dynamically Reconfigurable Asynchronous FPGA Architecture

This paper presents APL, an Asynchronous Programmable Logic array, as a flexible dynamically reconfigurable multi-application platform with self-reconfigurability. APL employs a Globally-Asynchronous-Locally-Syn-chronous (GALS) architecture. It consists of Timing Regions (TRs) which operate independently under locally generated clocks and communicate with each other through handshaking asynchronous interfaces. Different applications are mapped into different TRs, so they can run independently. And because of the asynchronous communication, dynamic partial reconfiguration is easily realized with TRs as the basic reconfiguration units. Self-reconfiguration is realized by giving each TR the capability to access the central configuration controller which, in turn, can read/write the configuration memory.