Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA

This paper deals with the FPGA-implementation of a high-speed interface for DDR SDRAMs. We aim to achieve a performance, in terms of bandwidth, comparable to ASIC implementations. The novelty of this paper is to present the design techniques that lead to high performance memory controllers. First of all, we compile the specific hardware features available in FPGA families. In the second place, we depict a memory interface data path architecture adapted for implementation on Xilinx and Altera FPGAs. Finally, we explain the design rules to meet timing requirements (round trip delay) for successful operation. The discussion is complemented with timing measurements for a Virtex-II based memory interface and with timing calculations performed for Stratix.