Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs

This work introduces three improvements to the traditional simulated annealing algorithm, which is widely used in industrial and academic tools for FPGA placement. The improved algorithm has been tested with the 20 largest benchmarks from the MCNC set and the results were compared with the VPR placer. The outcome is nearly 3% better timing and about 6% less swap moves in the kernel of the simulated annealing algorithm. The main positive result is the reduction of the run time of the simulated annealing algorithm without sacrificing the placement quality for combined routability and timing driven case. For most benchmarks, the quality of the final placement could even be improved despite using less swap moves.