Spiral inductor performance in deep-submicron bulk-CMOS with copper interconnects

Spiral inductor performance in deep-submicron bulk-CMOS with copper interconnects

This paper reviews design considerations for spiral inductors in bulk CMOS and reports investigations carried out in a commercial 0.18 /spl mu/m process using 6-layer copper metallization. Quality factors of approximately 8 are measured for 10 nH spirals operating between 1 and 2 GHz. Comparisons of...

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Hauptverfasser: Kuhn, W.B., Orsborn, A.W., Peterson, M.C., Kythakyapuzha, S.R., Hussein, A.I., Jun Zhang, Jianming Li, Shumaker, E.A., Nair, N.C.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
CMOS process
Copper
Design. Technologies. Operation analysis. Testing
Eddy currents
Electronics
Exact sciences and technology
Frequency
Inductance
Inductors
Integrated circuits
Magnetic devices
Microelectronic fabrication (materials and surfaces technology)
Modems
Q factor
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Spirals
Stacking
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Beschreibung
Zusammenfassung:This paper reviews design considerations for spiral inductors in bulk CMOS and reports investigations carried out in a commercial 0.18 /spl mu/m process using 6-layer copper metallization. Quality factors of approximately 8 are measured for 10 nH spirals operating between 1 and 2 GHz. Comparisons of Q and self-resonant frequency are provided for a variety of construction variables including with/without a patterned ground shield, metal-6 only versus stacking layers 3 thru 6, dense versus sparse vias, wide versus narrow traces, and with/without metal-fill.
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2002.1012073