A Note on Designing Logical Circuits Using SAT

A Note on Designing Logical Circuits Using SAT

We present a systematic procedure to synthesise and minimise digital circuits using propositional satisfiability. After encoding the truth table into a canonical sum of at most k different products, we seek its minimal satisfiable representation. We show how to use an interesting local search landsc...

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Bibliographische Detailangaben
1. Verfasser: Estrada, Giovani Gomez
Format: Buchkapitel
Sprache:eng
Schlagworte:
Algorithmics. Computability. Computer arithmetics
Applied sciences
Artificial intelligence
Bisection Algorithm
Combinatorial Circuit
Computer science
control theory
systems
Digital Circuit
Exact sciences and technology
Learning and adaptive systems
Local Search
Theoretical computing
Truth Table
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Beschreibung
Zusammenfassung:We present a systematic procedure to synthesise and minimise digital circuits using propositional satisfiability. After encoding the truth table into a canonical sum of at most k different products, we seek its minimal satisfiable representation. We show how to use an interesting local search landscape for this minimisation. This approach can be very useful since we can generate exact minimal solutions within reasonably computational resources.
ISSN:0302-9743
1611-3349
DOI:10.1007/3-540-36553-2_37