Bridging the Gap between Compilation and Synthesis in the DEFACTO System

The DEFACTO project – a Design Environment For Adaptive Computing TechnOlogy – is a system that maps computations, expressed in high-level languages such as C, directly onto FPGA-based computing platforms. Major challenges are the inherent flexibility of FPGA hardware, capacity and timing constraints of the target FPGA devices, and accompanying speed-area trade-offs. To address these, DEFACTO combines parallelizing compiler technology with behavioral VHDL synthesis tools, obtaining the complementary advantages of the compiler’s high-level analyses and transformations and synthesis’ binding, allocation and scheduling of low-level hardware resources. To guide the compiler in the search of a good solution, we introduce the notion of balance between the rates at which data is fetched from memory and accessed by the computation, combined with estimation from behavioral synthesis. Since FPGA-based designs offer the potential for optimizing memory-related operations, we have also incorporated the ability to exploit parallel memory accesses and customize memory access protocols into the compiler analysis.