Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs
This paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly expl...
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| description | This paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly exploits the Shift Register Logic (SRL) component of the Virtex family in order to implement the necessary complex data scheduling, leading to considerable area savings compared to the conventional implementation (based on a hard router), with no speed penalty. Our architecture uses bit parallel arithmetic and is fully scalable and parameterisable. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented. |
| doi_str_mv | 10.1007/978-3-540-45234-8_54 |
| format | Book Chapter |
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K</contributor><contributor>Constantinides, George A.</contributor><contributor>Y. K. Cheung, Peter</contributor><creatorcontrib>Benkrid, A.</creatorcontrib><creatorcontrib>Benkrid, K.</creatorcontrib><creatorcontrib>Crookes, D.</creatorcontrib><title>Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs</title><title>Field Programmable Logic and Application</title><description>This paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly exploits the Shift Register Logic (SRL) component of the Virtex family in order to implement the necessary complex data scheduling, leading to considerable area savings compared to the conventional implementation (based on a hard router), with no speed penalty. Our architecture uses bit parallel arithmetic and is fully scalable and parameterisable. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented.</description><subject>Applied sciences</subject><subject>Boundary Processing</subject><subject>Canonic Sign Digit</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Finite Impulse Response</subject><subject>Finite Impulse Response Filter</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal Boundary</subject><issn>0302-9743</issn><issn>1611-3349</issn><isbn>3540408223</isbn><isbn>9783540408222</isbn><isbn>3540452346</isbn><isbn>9783540452348</isbn><fulltext>true</fulltext><rsrctype>book_chapter</rsrctype><creationdate>2003</creationdate><recordtype>book_chapter</recordtype><recordid>eNotkE9PGzEQxd2_IqV8gx586dGt7bHX3mNKCURCgBCtuFmO15uYbnYXe9PCt-8E4otHM--9Gf0I-SL4N8G5-V4by4BpxZnSEhSzTqs35BNg56VRvSUzUQnBAFT97jDgVkp4T2YcuGS1UfBxL6pUZQ2vj8hJKQ8cH0gQspqRh5-xpHVPfd_Q5Xbs4jb2k5_S0NOhpZ5eDX9jRxfLW7pI3RQzneewSVMM0y5H-i9NG_pj2PWNz8_0AkO61K8pmu8TVk_09_L27uyeLm7O5-Uz-dD6rsSTw39Mfi3O7k4v2OX1-fJ0fslGaeTEfGtWITSthUbg4aHRJsoYlWhrPDkilKYx3BiQKGoaW2khBFZ6pbSvvYZj8vU1d_Ql-K7Nvg-puDGnLV7phNa8rkCgTr7qCo76dcxuNQx_ihPc7fE73OQAkXP3Qtvt8aMJDuF5eNzFMrm4dwWkln0XNn5ESMUBt1ZY4SrutKnhPx5bgwc</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Benkrid, A.</creator><creator>Benkrid, K.</creator><creator>Crookes, D.</creator><general>Springer Berlin / Heidelberg</general><general>Springer Berlin Heidelberg</general><general>Springer</general><scope>FFUUA</scope><scope>IQODW</scope></search><sort><creationdate>2003</creationdate><title>Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs</title><author>Benkrid, A. ; Benkrid, K. ; Crookes, D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-p272t-af7bccdf83d1166cd57e2ee41f9312e978dd707732cdfdd865111dfd5b45a9a53</frbrgroupid><rsrctype>book_chapters</rsrctype><prefilter>book_chapters</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Applied sciences</topic><topic>Boundary Processing</topic><topic>Canonic Sign Digit</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Finite Impulse Response</topic><topic>Finite Impulse Response Filter</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal Boundary</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Benkrid, A.</creatorcontrib><creatorcontrib>Benkrid, K.</creatorcontrib><creatorcontrib>Crookes, D.</creatorcontrib><collection>ProQuest Ebook Central - Book Chapters - Demo use only</collection><collection>Pascal-Francis</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Benkrid, A.</au><au>Benkrid, K.</au><au>Crookes, D.</au><au>Sousa, Jose T. de</au><au>Constantinides, Georg A</au><au>Cheung, Peter Y. K</au><au>Constantinides, George A.</au><au>Y. K. Cheung, Peter</au><format>book</format><genre>bookitem</genre><ristype>CHAP</ristype><atitle>Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs</atitle><btitle>Field Programmable Logic and Application</btitle><seriestitle>Lecture Notes in Computer Science</seriestitle><date>2003</date><risdate>2003</risdate><volume>2778</volume><spage>553</spage><epage>564</epage><pages>553-564</pages><issn>0302-9743</issn><eissn>1611-3349</eissn><isbn>3540408223</isbn><isbn>9783540408222</isbn><eisbn>3540452346</eisbn><eisbn>9783540452348</eisbn><abstract>This paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly exploits the Shift Register Logic (SRL) component of the Virtex family in order to implement the necessary complex data scheduling, leading to considerable area savings compared to the conventional implementation (based on a hard router), with no speed penalty. Our architecture uses bit parallel arithmetic and is fully scalable and parameterisable. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented.</abstract><cop>Germany</cop><pub>Springer Berlin / Heidelberg</pub><doi>10.1007/978-3-540-45234-8_54</doi><oclcid>166468709</oclcid><tpages>12</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0302-9743 |
| ispartof | Field Programmable Logic and Application, 2003, Vol.2778, p.553-564 |
| issn | 0302-9743 1611-3349 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_15509631 |
| source | Springer Books |
| subjects | Applied sciences Boundary Processing Canonic Sign Digit Electronics Exact sciences and technology Finite Impulse Response Finite Impulse Response Filter Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal Boundary |
| title | Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs |
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