Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs

This paper presents the design and implementation of a novel architecture for FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of signal boundaries filtering, which occurs in finite length signal processing (e.g. image processing). It cleverly exploits the Shift Register Logic (SRL) component of the Virtex family in order to implement the necessary complex data scheduling, leading to considerable area savings compared to the conventional implementation (based on a hard router), with no speed penalty. Our architecture uses bit parallel arithmetic and is fully scalable and parameterisable. A case study based on the implementation of the standard low filter of the Daubechies-8 wavelet on Xilinx Virtex-E FPGAs is presented.