ESD circuit simulation for the prevention of ESD failures: Application to products in a 0.18 μm CMOS technology

Bibliographische Detailangaben

Hauptverfasser:	WOLF, Heinrich, GIESER, Horst, STADLER, Wolfgang, ESMARK, Kai
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Testing, measurement, noise and reliability Transistors
Online-Zugang:	Volltext
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