Optimization of Run-Time Reconfigurable Embedded Systems

Run-time reconfigurable approaches for FPGAs are gaining interest as they enlarge the design space for system implementation by sequential execution of temporally exclusive system parts on one or several FPGA resources. In [7], we introduced a novel methodology and a design tool for communication synthesis in reconfigurable embedded systems. In [5], this work was extended by a hierarchical reconfiguration structure that implements reconfiguration control. In this paper, we describe techniques that are employed to optimize the reconfiration structure and its communication requirements. The optimizations reduce the required FPGA area and I/O pins.