Verified Optimizations for the Intel IA-64 Architecture

This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The formalization and proofs were carried out using the HOL Light theorem prover.

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Bibliographische Detailangaben
1. Verfasser:	Grundy, Jim
Format:	Buchkapitel
Sprache:	eng
Schlagworte:	Applied sciences Computer science control theory systems Electronics Exact sciences and technology Instruction Memory Integrated circuits Integrated circuits by function (including memories and processors) Intel Corporation Language processing and microprogramming Memory Region Page Fault Register File Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Software
Online-Zugang:	Volltext
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Beschreibung
Zusammenfassung:	This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The formalization and proofs were carried out using the HOL Light theorem prover.
ISSN:	0302-9743 1611-3349
DOI:	10.1007/3-540-44659-1_14