Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques

Today’s design community need tools that address early power estimation, making it possible to find the optimal design trade-offs without respinning to explore the whole chip. Several approaches based on a fast (coarse) logic synthesis step, in order to analyze power on the mapped gate-level netlist and then create suitable power models have been published in the last years. In this paper we present some applications of RTPow, a proprietary tool dealing with the RT-level power estimation. The innovative estimation engine that does not perform any type of on-the-fly logic synthesis, but analyze the HDL description from the functionality point of view, permits a drastic time saving. Besides this top-down estimation, RTPow is able to perform a series of power macromodels and the bottom-up approach that enable an effective power budgeting. The first is an Adaptive Gaussian Noise Filter (28K Eq.Gate), described in VHDL, the second is a Motion Estimation and Compensation Device for Video Field Rate Doubling Application (171K Eq.Gate) also described in VHDL. The third is a micro-processor core (111K Eq.Gate) described using Verilog language.