SEU mitigation for half-latches in xilinx virtex FPGAs

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field-programmable gate arrays (FPGAs) make them very interesting for high-speed, on-orbit data processing, but, because the current generation of radiation-tolerant SRAM-based FPGAs are derived directly from COTS versions of the chips, their memory structures are still susceptible to single-event upsets (SEUs) . While previous papers have described the SEU characteristics and mitigation techniques for the configuration and user memory structures on the Xilinx Virtex family of FPGAs, we will concentrate on the effects of SEUs on 'half-latch' structures within the Virtex architecture, describe techniques for mitigating these effects, and provide new experimental data which illustrate the effectiveness of one of these mitigation techniques under proton radiation.