Cell Multiprocessor Communication Network: Built for Speed

Multicore designs promise various power-performance and area-performance benefits. But inadequate design of the on-chip communication network can deprive applications of these benefits. To illuminate this important point in multicore processor design, the authors analyze the cell processor's co...

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Veröffentlicht in:	IEEE MICRO 2006-05, Vol.26 (3), p.10-23
Hauptverfasser:	Kistler, M., Perrone, M., Petrini, F.
Format:	Artikel
Sprache:	eng
Schlagworte:	ARRAY PROCESSORS Bandwidth Benchmarks Broadband Buildings CAPACITY Cell Broadband Engine processor Communication networks COMMUNICATIONS Communications networks Computer science Concurrent computing Delay DESIGN Energy consumption ENGINES EVALUATION High performance computing MANUFACTURERS Microprocessors Multicore processing multiprocessor communication network Network-on-a-chip PHYSICS OF ELEMENTARY PARTICLES AND FIELDS Process design PROCESSING Protocol (computers) RESOLUTION SIMULATORS SOLAR PROTONS Synchronism SYNCHRONIZATION Traffic engineering Traffic flow VELOCITY
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Beschreibung
Zusammenfassung:	Multicore designs promise various power-performance and area-performance benefits. But inadequate design of the on-chip communication network can deprive applications of these benefits. To illuminate this important point in multicore processor design, the authors analyze the cell processor's communication network, using a series of benchmarks involving various DMA traffic patterns and synchronization protocols
ISSN:	0272-1732 1937-4143
DOI:	10.1109/MM.2006.49