A new circuit model for tunneling related trapping at insulator-semiconductor interfaces in accumulation

We have investigated the effects due to the capture of tunneling electrons by interface traps to the measured capacitance, Cm, and equivalent series resistance, Rm, of insulator-semiconductor interfaces in metal-insulator-semiconductor (MIS) capacitors in accumulation. A new circuit model taking into account the capture of tunneling electrons by interface traps is derived. Theoretical and experimental results of Si3N4/Si/GaAs, Si3N4/epi-Si, and SiO2/epi-Si MIS capacitors are compared. The Si, Si3N4, and SiO2 layers investigated were deposited in situ by electron cyclotron resonance generated plasma in an ultrahigh vacuum chemical vapor deposition chamber. Frequency dispersion of both Cm and Rm can be adequately explained by the new circuit model.