Mapping nested loop algorithms into multidimensional systolic arrays

Mapping nested loop algorithms into multidimensional systolic arrays

Consideration is given to transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where 1

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Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on parallel and distributed systems 1990-01, Vol.1 (1), p.64-76
Hauptverfasser: Lee, P.-Z., Kedem, Z.M.
Format: Artikel
Sprache:eng
Schlagworte:
990200 - Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
Computer science
COMPUTERS
DESIGN
ELECTRONIC CIRCUITS
GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
GRAPHS
History
HYPERCUBE COMPUTERS
IMPLEMENTATION
Information science
INTEGRATED CIRCUITS
MANY-DIMENSIONAL CALCULATIONS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
Multidimensional systems
OPTIMIZATION
PARALLEL PROCESSING
PROGRAMMING
Sufficient conditions
Systolic arrays
THREE-DIMENSIONAL CALCULATIONS
Transmission line matrix methods
Vectors
Very large scale integration
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Beschreibung
Zusammenfassung:Consideration is given to transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where 1
ISSN:1045-9219
1558-2183
DOI:10.1109/71.80125