Fully symmetric cooled CMOS on (110) plane

A new cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10 super(14) cm super(-2), and no channel implant is described. It is found that the peak mobility of a p super(+) polysilicon gate pMOS transistor on a (110) plane is 1.6 times larger than that on a (100) plane at 77 K. This pMOS transistor is very promising for use at 77 K because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetric cooled CMOS devices with 0.8- mu m gates in which saturation currents and transconductances of both n and pMOS transistors have been almost equalized.